552 Discussion # 4
TA: Guangyu Shi
10/04/2010
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0. A few design issues
- Downside of clock gating
- Naming rule in Quartus and some other tips
- CLA hierarchical design example

1. Homework 2
- P1-2: check out discussion summary 3
- p4: We define ALU operates on signed values (and thus overflow for signed values. Good point.)
- CLA: using xor for propagate signal is simpler for adder. But in our case, using or gate may be better, because later we can use it to do the OR operation for ALU.

2. Course materials
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3. Other issues
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